Lateral Double-Diffused (LD) transistors have been widely employed in high voltage applications. One factor which affects the performance of the LD transistors is the gate to drain capacitance (Cgd). For example, lower Cgd enables faster switching of LDMOS drivers.
Conventional techniques in achieving low Cgd can result in increased drain-to-source on-resistance (Rdson), which, in turn, undesirably decreases switching speed.
The disclosure is directed to transistors with fast switching speed.